The size of process nodes continues to shrink. As a result, the related voltages which can be used to power devices in these nodes are lowered. In order to be backward compatible with legacy chips from previous generations and older standards, input/output (I/O) devices may be required that swing above the maximum ratings for the process used to create the devices.
While this may be easily achieved for input devices powered by a lower voltage, it may not be easy for output drivers, since the output drivers may require a higher voltage supply to source the necessary output current. This higher voltage supply may not be needed for input devices. Since the voltage of this higher voltage supply may be higher than the allowed maximum rating of the output devices, long-term reliability of the output devices may only be achieved by design and control of all voltages over the different transistors and devices.
However, this also means that ESD protection needs to allow for voltages across nodes of the devices used in the ESD protection that surpass the maximum rating of the devices defined by the process. When the voltage of the voltage supply exceeds the maximum rating of the devices powered by the supply, the need for a new type of ESD clamp arises.
The problem of long-term reliability when using a single stage MOS device may be overcome by stacking the MOS transistors and thus dividing the ‘overvoltage’ to levels within the maximum ratings. Traditional stacked MOS devices and various ways to drive these to maximize their current driving capabilities are widely known. However, in most cases, the stacked MOS devices may share the same bulk for bipolar action, thus exposing at least one drain junction to an ‘overvoltage’. Hence stacking more than 2 MOS devices may not be possible.
FIG. 1a depicts a schematic of a traditional ESD clamp 100. An NMOS 103 may have its gate 103a connected to the source 103b, turning it off. As understood by one skilled in the art, the gate of a grounded gate NMOS (ggNMOS) may be coupled to its source which may turn off the channel of the NMOS. Because its channel is off, a rather high voltage may be needed to turn on the parasitic NPN between drain 103c and source 103b (and bulk 103d). In another traditional ESD clamp 110, as depicted in FIG. 1b, the NMOS 110 may be RC-triggered. By means of a resistor 115, the gate node 113a may be pulled to its source 113b during normal operation. When an ESD event occurs, the transient voltage at the anode 111 may be transferred to the gate 113a through the capacitor 114 if the capacitor value is correctly chosen, and the biased gate may turn on the channel, thus allowing for triggering at a lower voltage than the clamp 100.
FIG. 2 depicts an example of a commonly known overvoltage-tolerant circuit often used in drivers. The stack 207 of 2 or more MOS transistors 203 and 204 may allow for voltages above nominal on the anode 201 without failure, while at the same time the stacked arrangement may deliver the protection as described above with a single MOS transistor. Besides the two parasitic NPNs in the two MOS devices 203 and 204 formed between their respective drains and sources (and bulk), a third parasitic may exist between the drain 204c of the upper MOS 204 and the source of the lower MOS 203b. This may act as a single bipolar, similar to the parasitic bipolar formed by configuration shown in FIGS. 1a and 1b, in parallel with the stack of the 2 parasitic bipolar transistors. In order to avoid overstress of the individual transistors 203 and 204, the gate 204a of the transistor 204 may be tied to a positive supply voltage 206. The drain 204c may be directly connected with the anode 201. MOS 203 may be used as an output driver wherein the gate 203a of MOS 203 may be used for signaling and to control the overall behavior of the stack. For the circuit depicted in FIG. 2, the gate 203a may also be grounded to increase the trigger voltage of circuit 200. The source 203b may be directly connected with the ground line. In general, transistors 203 and 204 may share a common substrate node through the substrate connection 203d and 204d to allow for single bipolar turn-on mode and a sufficient low holding voltage. To protect the upper drain-bulk junction 204c-204d or source-bulk junction 204b-204d or lower drain-bulk junction 203c-203d, any local silicidation (fully or partially, if any) may be blocked corresponding to the portions outlined by dotted line 205 to prevent any intra- or inter-finger trigger issues.
Circuit 200 may be appropriate for use as an overvoltage-tolerant circuit where the voltage at the IO pin can be larger than the voltage at VDD for small periods. However, it may not be a reliable solution when applied to an ‘overvoltage’ power domain, wherein the voltage of the power domain is permanently higher than the maximum voltage rating for a single transistor.